Skip to main navigation Skip to search Skip to main content

Rapid single-chip secure processor prototyping on the Open SPARC FPGA platform

  • Jakub M. Szefer
  • , Wei Zhang
  • , Yu-Yuan Chen
  • , David Champagne
  • , King Chan
  • , Will X. Y. Li
  • , Ray C. C. Cheung
  • , Ruby B. Lee

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

Abstract

Secure processors have become increasingly important for trustworthy computing as security breaches escalate. By providing hardware-level protection, a secure processor ensures a safe computing environment where confidential data and applications can be protected against both hardware and software attacks. In this paper, we present a single-chip secure processor model and demonstrate rapid prototyping of the secure processor on the OpenSPARC FPGA platform. OpenSPARC T1 is an industry-grade, open-source, FPGA-synthesizable general-purpose microprocessor originally developed by Sun Microsystems, now acquired by Oracle. It is a multi-core, multi-threaded 64-bit processor with open-source hardware, including the microprocessor core, as well as system software that can be freely modified by researchers. We modify the OpenSPARC T1 processor by adding security modules: an AES engine, a TRNG and a memory integrity tree. These enhancements enable security features like memory encryption and memory integrity verification. By prototyping this single-chip secure processor on the FPGA platform, we find that the OpenSPARC T1 FPGA platform has many advantages for secure processor research. Our prototyping demonstrates that additional modules can be added quickly and easily and they add little resource overhead to the base OpenSPARC processor. © 2011 IEEE.
Original languageEnglish
Title of host publicationProceedings of the International Workshop on Rapid System Prototyping
Pages38-44
DOIs
Publication statusPublished - 2011
Event2011 22nd IEEE International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP-2011 - Karlsruhe, Germany
Duration: 24 May 201127 May 2011

Publication series

Name
ISSN (Print)1074-6005

Conference

Conference2011 22nd IEEE International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP-2011
PlaceGermany
CityKarlsruhe
Period24/05/1127/05/11

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

  1. SDG 9 - Industry, Innovation, and Infrastructure
    SDG 9 Industry, Innovation, and Infrastructure

Fingerprint

Dive into the research topics of 'Rapid single-chip secure processor prototyping on the Open SPARC FPGA platform'. Together they form a unique fingerprint.

Cite this