Race to idle or not : Balancing the memory sleep time with DVS for energy minimization

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)

2 Scopus Citations
View graph of relations

Author(s)

Related Research Unit(s)

Detail(s)

Original languageEnglish
Title of host publicationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-18
ISBN (Electronic)9783981537055
ISBN (Print)9783981537048
Publication statusPublished - Mar 2015

Publication series

NameDesign, automation and test in Europe conference
Volume2015
ISSN (Print)1530-1591
ISSN (Electronic)1558-1101

Conference

Title2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PlaceFrance
CityGrenoble
Period9 - 13 March 2015

Abstract

Reducing energy consumption is a critical problem in most of the computing systems today. In recent years, dynamic voltage scaling (DVS) has been often applied in the multi-core processor systems. The leakage power of the main memory shared by the multiple DVS cores is becoming a larger problem with technology scaling. This paper focuses on minimizing the system-wide energy consumption by applying DVS on each core and turning the memory to sleep when all the cores have common idle time. This work presents systematic analysis for the target problem based on different system models and task models. For tasks with common release time, optimal schemes are presented for the systems both with and without considering the static power of the cores. For the general task model, a heuristic online algorithm is proposed. Furthermore, the scheme is extended to handle the problem when the transition overhead between the active and sleep modes is not negligible. The experimental results show that the heuristic algorithm can reduce the energy consumption of the overall system by 8.73% in average (up to 28.44%) compared to a state-of-the-art multi-core DVS scheduling scheme.

Citation Format(s)

Race to idle or not : Balancing the memory sleep time with DVS for energy minimization. / Fu, Chenchen; Li, Minming; Xue, Chun Jason.

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). Institute of Electrical and Electronics Engineers Inc., 2015. p. 13-18 7092351 (Design, automation and test in Europe conference; Vol. 2015).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)