Content-addressable memory (CAM) is a searching memory which provides the address of the search key in a single clock cycle. High speed lookup operation of CAM makes it extremely attractive in security, in-memory computing, distributed systems and networking applications. Field programmable gate arrays (FPGAs) are famous for hardware-like performance and software-like re-configurability, but it does not have built-in CAM. Researchers have used different hardware components, like Block random-access memory (RAM), distributed RAM, flip-flops etc., to emulate the functionality of CAM inside FPGAs. This paper presents the design space exploration of gate-based area efficient ternary content addressable memory (GAETCAM) which uses flip-flops as memory elements on FPGA and can be configured as binary as well as ternary CAM. By configuring G-AETCAM as binary CAM, due to the redundancy of masking bits, half of the resources on FPGA are saved. We have implemented different sizes of G-AETCAM on Xilinx Virtex-5, Virtex-6 and Virtex-7 FPGAs and provided the results in detail for the designers to choose according to the application’s requirements. Throughput, as a critical performance metric, is improved by 28% compared to other FPGA-based TCAM counterparts. Moreover, scalability is shown as a trade-off of G-AETCAM due to the routing complexity of the architecture and the factors limiting the largest possible size on each FPGA device are reported in this work.