VLSI implementation of genetic four-step search for block matching algorithm

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Pages (from-to)1474-1481
Journal / PublicationIEEE Transactions on Consumer Electronics
Issue number4
Publication statusPublished - Nov 2003


Genetic algorithm is well known for searching global optimum. It has been demonstrated its capability for Block Motion Estimation with performance close to exhaustive full search using fewer search steps. However, it is computational expensive. A Genetic Four-Step Search is developed to alleviate the problem. It has a mean square error performance close to full search and much computational efficient than the traditional genetic algorithm. A FPGA implementation of the proposed algorithm is realized. The architecture is simple and suitable for valuable applications in the development of low cost multimedia products.

Research Area(s)

  • Block matching algorithm, FPGA, VLSI