Manipulating III-V Nanowire Transistor Performance via Surface Decoration of Metal-Oxide Nanoparticles

Recently, III–V semiconductor nanowires (NWs) are widely investigated as field-effect transistors (FETs) for high-performance electronics, optoelectronic, and others; nevertheless, effective control in their device performances, especially the threshold voltage is still not well attained, which can potentially limit their practical uses for technological applications. This study reports a simple but highly reliable metal-oxide nanoparticle (NP) surface decoration approach onto the device channel in order to manipulate electrical characteristics of III–V NWFETs, such as the threshold voltage and transistor operation, through the manipulation of free electrons in the NW channel (i.e., InAs, InP, and In_0.7Ga_0.3As) via depositing various metal-oxide NPs with different work functions. Without any passivation layer, this decoration approach can yield the stable NW device characteristics in ambient. Notably, the versatility of our decoration scheme has also been illustrated through the realization of high-performance enhancement-mode InAs NW-paralleled-arrayed devices as well as the configuration of highly efficient InAs NW NMOS inverters, comprising of both depletion and enhancement mode devices. All these results further elucidate the technological potential of this decoration approach for future high-performance, low-power nanoelectronic device fabrication, and circuit integration.