Hardware implementation of genetic algorithms using FPGA

Research output: Journal Publications and ReviewsRGC 22 - Publication in policy or professional journal

40 Scopus Citations
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Original languageEnglish
Journal / PublicationMidwest Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2004

Conference

TitleThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings
PlaceJapan
CityHiroshima
Period25 - 28 July 2004

Abstract

In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.