Adaptively Biased 60-GHz Doherty Power Amplifier in 65-nm CMOS
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
Original language | English |
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Article number | 7865996 |
Pages (from-to) | 296-298 |
Journal / Publication | IEEE Microwave and Wireless Components Letters |
Volume | 27 |
Issue number | 3 |
Publication status | Published - 1 Mar 2017 |
Link(s)
Abstract
A 60-GHz Doherty power amplifier (PA) implemented in 65-nm bulk CMOS process is proposed. A novel adaptive biasing network is devised to dynamically adjust the bias voltage of the peaking PA, counteracting its low transconductance caused by the class-C biasing condition. At 60 GHz, the fabricated Doherty PA achieves 22% drain efficiency with a saturation power of 13.2 dBm. The measured results show that over 17% and 8% efficiencies at peak and 6-dB back-off power regions are achieved, respectively, from 57 to 64 GHz.
Research Area(s)
- Adaptive biasing, cascode, Doherty power amplifier (PA), millimeter-wave (mm-wave) CMOS, power-added efficiency
Citation Format(s)
Adaptively Biased 60-GHz Doherty Power Amplifier in 65-nm CMOS. / Chen, Shichang; Wang, Gaofeng; Cheng, Zhiqun et al.
In: IEEE Microwave and Wireless Components Letters, Vol. 27, No. 3, 7865996, 01.03.2017, p. 296-298.
In: IEEE Microwave and Wireless Components Letters, Vol. 27, No. 3, 7865996, 01.03.2017, p. 296-298.
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review