A fully integrated architecture for fast programming of floating gates
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
Author(s)
Detail(s)
Original language | English |
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Article number | 4252795 |
Pages (from-to) | 957-960 |
Journal / Publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Publication status | Published - 2007 |
Externally published | Yes |
Conference
Title | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 |
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Place | United States |
City | New Orleans, LA |
Period | 27 - 30 May 2007 |
Link(s)
Abstract
We present an on-chip system that enables programming floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring ADC operating over 4 decades at 10bit accuracy or 7decades at 7 bit accuracy. The conversion time is around 200 μs till around 30 pA of current. The gate and drain voltages are set by on-chip DACs. The digital words for the DAC are sent by an FPGA through an SPI interface. The controller for sequencing the operations as well as the look-up-table with characterization data are on the FPGA. Algorithms using either pulse-width modulation or drain voltage modulation can be implemented. © 2007 IEEE.
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Citation Format(s)
A fully integrated architecture for fast programming of floating gates. / Basu, Arindam; Hasler, Paul.
In: Proceedings - IEEE International Symposium on Circuits and Systems, 2007, p. 957-960.
In: Proceedings - IEEE International Symposium on Circuits and Systems, 2007, p. 957-960.
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review