Pseudo-TCAM : SRAM-Based Architecture for Packet Classification in One Memory Access

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Pages (from-to)89-92
Journal / PublicationIEEE Networking Letters
Issue number2
Online published6 Feb 2019
Publication statusPublished - Jun 2019


A SRAM-based hardware architecture that emulates the behavior of ternary content addressable memory for packet classification is presented. Header fields of the packet are encoded using the prefix inclusion coding method. Encoded rules are mapped to SRAM-based match units using a bit-selection approach. Selected bits of the input key are used as the address to access a rule in the SRAM for comparison. The average memory cost is 26.3 and 18.5 bytes per rule for rulesets with 10K and 100K rules, respectively. The proposed method is implemented on Xilinx UltraScale FPGA. Throughput of the classifier can reach 426 million packets per second.