Pseudo-TCAM : SRAM-Based Architecture for Packet Classification in One Memory Access
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 89-92 |
| Journal / Publication | IEEE Networking Letters |
| Volume | 1 |
| Issue number | 2 |
| Online published | 6 Feb 2019 |
| Publication status | Published - Jun 2019 |
Link(s)
| DOI | DOI |
|---|---|
| Permanent Link | https://scholars.cityu.edu.hk/en/publications/publication(0f60d2e7-1145-4d2a-8a39-2f65aa127dce).html |
Abstract
A SRAM-based hardware architecture that emulates
the behavior of ternary content addressable memory for packet
classification is presented. Header fields of the packet are
encoded using the prefix inclusion coding method. Encoded rules
are mapped to SRAM-based match units using a bit-selection
approach. Selected bits of the input key are used as the address to
access a rule in the SRAM for comparison. The average memory
cost is 26.3 and 18.5 bytes per rule for rulesets with 10K and
100K rules, respectively. The proposed method is implemented on
Xilinx UltraScale FPGA. Throughput of the classifier can reach
426 million packets per second.
Citation Format(s)
Pseudo-TCAM : SRAM-Based Architecture for Packet Classification in One Memory Access. / Yu, Weiwen; Sivakumar, Srinivas; Pao, Derek.
In: IEEE Networking Letters, Vol. 1, No. 2, 06.2019, p. 89-92.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
