TY - GEN
T1 - Profit maximization through process variation aware high level synthesis with speed binning
AU - Zhao, Mengying
AU - Alex, Orailoglu
AU - Jason, Xue Chun
N1 - Full text of this publication does not contain sufficient affiliation information. Research Unit(s) information for this record is based on his previous affiliation.
PY - 2013
Y1 - 2013
N2 - As integrated circuits continuously scale up, process variation plays an increasingly significant role in system design and semiconductor economic return. In this paper, we explore the potential of profit improvement under the inherent semiconductor variability based on the speed binning technique. We first accordingly propose a set of high level synthesis techniques, including allocation, scheduling and resource binding, thus essentially constructing designs that maximize the number of chips that can be sold at the most advantageous price, leading to the maximization of the overall profit. We explore subsequently the optimal bin placement strategy for further profit improvement. Experimental results confirm the superiority of the high level synthesis results and the associated improvement in profit margins. © 2013 EDAA.
AB - As integrated circuits continuously scale up, process variation plays an increasingly significant role in system design and semiconductor economic return. In this paper, we explore the potential of profit improvement under the inherent semiconductor variability based on the speed binning technique. We first accordingly propose a set of high level synthesis techniques, including allocation, scheduling and resource binding, thus essentially constructing designs that maximize the number of chips that can be sold at the most advantageous price, leading to the maximization of the overall profit. We explore subsequently the optimal bin placement strategy for further profit improvement. Experimental results confirm the superiority of the high level synthesis results and the associated improvement in profit margins. © 2013 EDAA.
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U2 - 10.7873/date.2013.050
DO - 10.7873/date.2013.050
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 978-1-4673-5071-6
SP - 176
EP - 181
BT - Proceedings - Design, Automation and Test in Europe
PB - IEEE
T2 - 16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013)
Y2 - 18 March 2013 through 22 March 2013
ER -