Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

13 Scopus Citations
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Detail(s)

Original languageEnglish
Pages (from-to)310-321
Journal / PublicationIEEE Transactions on Reliability
Volume69
Issue number1
Online published15 Feb 2019
Publication statusPublished - Mar 2020

Abstract

With the rapid development of technology scaling and cell density improvement for capacity increase and cost reduction, nand flash memory is confronted with degraded reliability. On one hand, while low-density parity-check (LDPC) codes have been deployed in today’s nand flash memories to enhance reliability, flash read latency has still been a performance bottleneck with the increased raw bit error rates (RBER). On the other hand, significant process variations (PV) have been found on existing nand flash memories, which introduce great reliability variations among different flash blocks. Recent studies have proposed to exploit PV to improve endurance by better wear leveling or to improve write performance. These approaches are prone to allocate read data to blocks with low reliability, which further degrades read performance. This paper proposes to enhance read performance of LDPC-equipped nand flash memory by exploiting the reliability variations from PV. The paper consists of three parts. First, a block grouping approach is presented to categorize flash blocks according to their reliability. Second, according to the grouping scheme, a data placement scheme is proposed, which allocates read-hot data to flash blocks with high reliability. At the same time, the read-cold data is moved to blocks with low reliability. As a result, the read performance is enhanced. However, allocating high reliable blocks for read-hot data collides with previous PV-based wear leveling methods. To address the issue, the third part is a grouping partition scheme which limits the amount of high reliable blocks occupied by read-hot data. Therefore, read performance enhancement can be achieved and the wear leveling schemes will be impacted slightly. Experiment results present that, the proposed approach can provide significant read performance improvement on LDPC-equipped nand flash memory and is compatible with the previous PV-based wear leveling.

Research Area(s)

  • Computer science, Decoding, Error correction, Error correction codes, Iterative decoding, Low-density parity-check (LDPC) codes, nand flash memory, process variation (PV), read performance, Reliability

Citation Format(s)

Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory. / Li, Qiao; Shi, Liang; Di, Yejia et al.
In: IEEE Transactions on Reliability, Vol. 69, No. 1, 03.2020, p. 310-321.

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review