Planarizing a-C:H and SiO2 films prepared by bias electron cyclotron resonance plasma deposition
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review
Author(s)
Detail(s)
Original language | English |
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Title of host publication | Proceedings. Sixth International IEEE VLSI Multilevel Interconnection Conference |
Publisher | Institute of Electrical and Electronics Engineers, Inc. |
Pages | 65-71 |
Publication status | Published - Jun 1989 |
Externally published | Yes |
Conference
Title | Sixth International VLSI Multilevel Interconnection Conference |
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Place | United States |
City | Santa Clara, CA |
Period | 12 - 13 June 1989 |
Link(s)
Abstract
Room-temperature bias electron cyclotron resonance plasma deposition of both carbon- and silicon-based planarization materials has been demonstrated. Planarization layers of amorphous hydrogenated carbon (a-C:H) have been deposited from 1-butene and 1,3-butadiene. Oxide and aluminum features 1-μm deep by 2-μm wide have been planarized to less than 50 nm in height using 1.2-μm-thick a-C:H films. Silicon dioxide layers have been deposited using a mixture of N2O, Ar, and 5% SiH4 diluted in N2. Using films nominally 1.5 μm thick, 800-nm-deep topography can be reduced to less than 50 nm for lines as wide as 3 μm. The planarizing SiO2 layers have been characterized using ellipsometry and Auger electron spectroscopy and found to have a refractive index and stoichiometry comparable to those of thermally grown gate oxide. The time necessary for planarization and the final film thickness are dependent upon the aspect ratio of the features to be planarized and the deposition conditions.
Citation Format(s)
Planarizing a-C:H and SiO2 films prepared by bias electron cyclotron resonance plasma deposition. / Horn, M. W.; Pang, S. W.; Rothschild, M. et al.
Proceedings. Sixth International IEEE VLSI Multilevel Interconnection Conference. Institute of Electrical and Electronics Engineers, Inc., 1989. p. 65-71.
Proceedings. Sixth International IEEE VLSI Multilevel Interconnection Conference. Institute of Electrical and Electronics Engineers, Inc., 1989. p. 65-71.
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review