Pipelined modified booth multiplication

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Detail(s)

Original languageEnglish
Pages (from-to)51-54
Journal / PublicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3
Publication statusPublished - 1998

Conference

Title1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98)
LocationInstituto Superior Técnico
PlacePortugal
CityLisboa
Period7 - 10 September 1998

Abstract

A pipelined modified Booth multiplication is proposed to enhance the power performance ratio of 2's complement multiplication. System architecture of the proposed scheme is catered for VLSI implementation. It is designed with the merit of low power consumption achieved by reducing the number of adder required. Only half of the adders is required as in traditional pipelined multiplier.