TY - JOUR
T1 - Pipelined architecture for multi-string matching
AU - Pao, Derek
AU - Lin, Wei
AU - Liu, Bin
PY - 2008/2
Y1 - 2008/2
N2 - We present a pipelined approach to hardware implementation of the Aho-Corasick (AC) algorithm for string matching called P-AC. By incorporating pipelined processing, the state graph is reduced to a character trie that only contains forward edges. Edge reduction in P-AC is very impressive and is guaranteed algorithmically. For a signature set with 4434 strings extracted from the Snort rule set, the memory cost of P-AC is only 21.5 bite/char. The simplicity of the pipeline control plus the availability of 2-port memories allow us to implement two pipelines sharing the set of lookup tables on the same device. By doing so, the system throughput can be doubled with little overhead. The throughput of our method is up to 8.8 Gbps when the system is implemented using 550MHz FPGA.
AB - We present a pipelined approach to hardware implementation of the Aho-Corasick (AC) algorithm for string matching called P-AC. By incorporating pipelined processing, the state graph is reduced to a character trie that only contains forward edges. Edge reduction in P-AC is very impressive and is guaranteed algorithmically. For a signature set with 4434 strings extracted from the Snort rule set, the memory cost of P-AC is only 21.5 bite/char. The simplicity of the pipeline control plus the availability of 2-port memories allow us to implement two pipelines sharing the set of lookup tables on the same device. By doing so, the system throughput can be doubled with little overhead. The throughput of our method is up to 8.8 Gbps when the system is implemented using 550MHz FPGA.
KW - Deterministic finite automaton
KW - Network intrusion detection
KW - Pipelined processing
KW - String matching
UR - http://www.scopus.com/inward/record.url?scp=58749084322&partnerID=8YFLogxK
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U2 - 10.1109/L-CA.2008.5
DO - 10.1109/L-CA.2008.5
M3 - RGC 21 - Publication in refereed journal
SN - 1556-6056
VL - 7
SP - 33
EP - 36
JO - IEEE Computer Architecture Letters
JF - IEEE Computer Architecture Letters
IS - 2
M1 - 4537166
ER -