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Pass-transistor logic and its sub-Vdd voltage-swing behaviours in low-voltage circuit design

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

Internal signal propagation with voltage swing less than the supply voltage have been proposed through various architecture or structures. And, reduced supply voltage in digital and analog circuits is considered to be one of the best methods to achieve real low power dissipation circuits. In this paper, pass-transistor logic with suppressed internal voltage-swing is investigated and analyzed. A proposal on reduced swing 14-bit parity generator, and a carry generation blocks of parallel full adder are also given. In addition, optimization on propagation delay can be achieved by proper tapering of dimension of transistors.
Original languageEnglish
Title of host publication1995 IEEE TENCON IEEE Region 10 Annual International Conference on Microelectronics and VLSI “Asia-Pacific Microelectronics 2000”
Subtitle of host publicationProceedings
PublisherIEEE
Pages307-310
ISBN (Print)0-7803-2624-5
DOIs
Publication statusPublished - 1995
Event1995 IEEE Region 10 International Conference on Microelectronics and VLSI (TENCON'95): “Asia-Pacific Microelectronics 2000” - Hong Kong Convention and Exhibition Centre, Hong Kong, China
Duration: 6 Nov 1995 → 10 Nov 1995

Conference

Conference1995 IEEE Region 10 International Conference on Microelectronics and VLSI (TENCON'95)
Abbreviated titleIEEE TENCON’95
PlaceHong Kong, China
Period6/11/95 → 10/11/95

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