OPTIMIZATION TECHNIQUES FOR HIGH ORDER PHASE-LOCKED LOOP TYPE JITTER REDUCTION CIRCUIT FOR DlGlTAL AUDIO

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

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Original languageEnglish
Pages (from-to)156-163
Journal / PublicationIEEE Transactions on Consumer Electronics
Volume42
Issue number1
Publication statusPublished - Feb 1996

Abstract

Techniques like gain peaking reduction and the selection of voltage-controlled-crystaloscillator's (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better sampling jitter attenuation when compared with that using maximum phase margin.