OPTIMIZATION TECHNIQUES FOR HIGH ORDER PHASE-LOCKED LOOP TYPE JITTER REDUCTION CIRCUIT FOR DlGlTAL AUDIO
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 156-163 |
| Journal / Publication | IEEE Transactions on Consumer Electronics |
| Volume | 42 |
| Issue number | 1 |
| Publication status | Published - Feb 1996 |
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Abstract
Techniques like gain peaking reduction and the selection of voltage-controlled-crystaloscillator's (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better sampling jitter attenuation when compared with that using maximum phase margin.
Citation Format(s)
OPTIMIZATION TECHNIQUES FOR HIGH ORDER PHASE-LOCKED LOOP TYPE JITTER REDUCTION CIRCUIT FOR DlGlTAL AUDIO. / Wong, W. K.
In: IEEE Transactions on Consumer Electronics, Vol. 42, No. 1, 02.1996, p. 156-163.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal
