TY - JOUR
T1 - OPTIMIZATION TECHNIQUES FOR HIGH ORDER PHASE-LOCKED LOOP TYPE JITTER REDUCTION CIRCUIT FOR DIGITAL AUDIO
AU - Wong, W. K.
PY - 1995
Y1 - 1995
N2 - Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.
AB - Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.
UR - http://www.scopus.com/inward/record.url?scp=0029228641&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0029228641&origin=recordpage
U2 - 10.1109/ICCE.1995.518023
DO - 10.1109/ICCE.1995.518023
M3 - RGC 22 - Publication in policy or professional journal
SN - 0747-668X
VL - 14
SP - 362
EP - 363
JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
T2 - 1995 IEEE International Conference on Consumer Electronics
Y2 - 7 June 1995 through 9 June 1995
ER -