Optimal burn-in decision making

Taeho Kim, Way Kuo*

*Corresponding author for this work

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

16 Citations (Scopus)

Abstract

This paper presents a conceptual model of burn-in decision making which gives an optimal burn-in time for semiconductor devices and describes how burn-in affects total yield and reliability. For the gate oxide of integrated circuits we consider four burn-in policies: no burn-in, wafer-level bum-in only, package-level burn-in only and wafer-level burn-in prior to package-level burn-in. A decision-making model to minimize cost is given for each burn-in policy. Burn-in time is strongly limited by the cost factor and reliability requirements. In order to reduce the cost incurred in burn-in, a short test time and small test samples are recommended. © 1998 John Wiley & Sons, Ltd.
Original languageEnglish
Pages (from-to)417-423
JournalQuality and Reliability Engineering International
Volume14
Issue number6
DOIs
Publication statusPublished - Nov 1998
Externally publishedYes

Research Keywords

  • Burn-in
  • Package-level burn-in
  • Semiconductor devices
  • Wafer-level burn-in

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