TY - GEN
T1 - On optimum designs of universal switch blocks
AU - Fan, Hongbing
AU - Liu, Jiping
AU - Wu, Yu-Liang
AU - Cheung, Chak-Chung
PY - 2002
Y1 - 2002
N2 - This paper presents a breakthrough decomposition theorem on routing topology and its applications in the designing of universal switch blocks. A switch block of k sides and W terminals on each side is said to be universal (a (k, W)-USB) if it is routable for every set of 2-pin nets with channel density at most W. The optimum USB design problem is to design a (k, W)-USB with the minimum number of switches for every pair of (k, W). The problem was originated from designing better k sides switch modules for 2D-FPGAs, such as Xilinx XC4000-type FPGAs, where k > 4. The interests in the generic USBs come from their potential usages in multi-dimensional and some non-conventional 2D-FPGA architectures, and as an individual switch components. The optimum (k, W)-USB was solved previously for even W, but left open for odd W. Our new decomposition theorem states that when W (> +3-i), a (k, W) routing requirement ((k, W)-RR) can be decomposed into one (k,k+3-i/3)-RR and 3W-k+i-3/6(k, 2)-RRs, where 1 > i > 6 and k = i (mod 6). By this theorem and the previously established reduction design scheme, the USB design problem is reduced to its minimum kernel designs, that enables us to design the best approximated (k, W)-USBs for all odd W. We also run extensive routing experiments using the currently best known FPGA router VPR, and the MCNC circuits with the conventional disjoint switch blocks and two kinds of universal switch blocks. The experimental results show that both kinds of USBs consistently improve the entire chip routability by over 6% than the conventional switch blocks. © Springer-Verlag Berlin Heidelberg 2002.
AB - This paper presents a breakthrough decomposition theorem on routing topology and its applications in the designing of universal switch blocks. A switch block of k sides and W terminals on each side is said to be universal (a (k, W)-USB) if it is routable for every set of 2-pin nets with channel density at most W. The optimum USB design problem is to design a (k, W)-USB with the minimum number of switches for every pair of (k, W). The problem was originated from designing better k sides switch modules for 2D-FPGAs, such as Xilinx XC4000-type FPGAs, where k > 4. The interests in the generic USBs come from their potential usages in multi-dimensional and some non-conventional 2D-FPGA architectures, and as an individual switch components. The optimum (k, W)-USB was solved previously for even W, but left open for odd W. Our new decomposition theorem states that when W (> +3-i), a (k, W) routing requirement ((k, W)-RR) can be decomposed into one (k,k+3-i/3)-RR and 3W-k+i-3/6(k, 2)-RRs, where 1 > i > 6 and k = i (mod 6). By this theorem and the previously established reduction design scheme, the USB design problem is reduced to its minimum kernel designs, that enables us to design the best approximated (k, W)-USBs for all odd W. We also run extensive routing experiments using the currently best known FPGA router VPR, and the MCNC circuits with the conventional disjoint switch blocks and two kinds of universal switch blocks. The experimental results show that both kinds of USBs consistently improve the entire chip routability by over 6% than the conventional switch blocks. © Springer-Verlag Berlin Heidelberg 2002.
KW - FPGA architecture
KW - Routing
KW - Universal switch block
UR - https://www.scopus.com/pages/publications/33947163787
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-33947163787&origin=recordpage
U2 - 10.1007/3-540-46117-5_16
DO - 10.1007/3-540-46117-5_16
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9783540441083
T3 - Lecture Notes in Computer Science
SP - 142
EP - 151
BT - Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream
A2 - Glesner, Manfred
A2 - Zipf, Peter
A2 - Renovell, Michel
PB - Springer
CY - Berlin, Heidelberg
T2 - 12th International Conference on Field-Programmable Logic and Applications (FPL 2002)
Y2 - 2 September 2002 through 4 September 2002
ER -