NOVEL SILICIDED SHALLOW JUNCTION TECHNOLOGY FOR CMOS VLSI.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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Author(s)

  • D. L. Kwong
  • Y. H. Ku
  • S. K. Lee
  • N. S. Alvi
  • P. Zhou
  • J. M. White

Detail(s)

Original languageEnglish
Title of host publicationMaterials Research Society Symposia Proceedings
PublisherMaterials Research Soc
Pages379-385
Volume71
ISBN (Print)931837375
Publication statusPublished - 1986
Externally publishedYes

Publication series

Name
Volume71
ISSN (Electronic)0272-9172

Abstract

A novel technique for the fabrication of shallow, silicided p plus -n junctions with excellent electrical characteristics has been developed. The technique utilizes the ion implantation of dopants into silicide layers formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of implanted dopants into the Si substrates to form shallow junctions. This technique can be easily applied to the fabrication of MOSFETs in a self-aligned fashion, and can have a significant impact on CMOS VLSI technology.

Citation Format(s)

NOVEL SILICIDED SHALLOW JUNCTION TECHNOLOGY FOR CMOS VLSI. / Kwong, D. L.; Ku, Y. H.; Lee, S. K.; Alvi, N. S.; Chu, P.; Zhou, P.; White, J. M.

Materials Research Society Symposia Proceedings. Vol. 71 Materials Research Soc, 1986. p. 379-385.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review