Nonlinearities and chaos in NMOS phase-locked loop

W. K. Siu, H. Wong, T. S. Cheung

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

Abstract

In this work, the nonlinearities and their induced chaotic characteristics of an integrated NMOS phase-locked loop (PLL) circuit are studied. Broadband chaotic spectra are observed in both locked and unlocked states. A mathematical model that describes accurately the dynamic behaviors of the PLL system is derived. By using Melnikov's method, the region of chaos generation in the PLL system is determined analytically. The theoretical prediction agrees well with the simulation results.
Original languageEnglish
Title of host publicationInternational Symposium on IC Technology, Systems and Applications
Pages262-265
Volume7
Publication statusPublished - 1997
Event7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
Duration: 10 Sept 199712 Sept 1997

Publication series

Name
Volume7

Conference

Conference7th International Symposium on IC Technology, Systems and Applications ISIC 97
PlaceSingapore
CitySingapore
Period10/09/9712/09/97

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