Abstract
A pipelined modified Booth multiplication is proposed for low power, high performance DSP application. The proposed multiplication is suitable for VLSI implementation. It has a better power-performance ratio than the traditional pipelined multiplier and modified Booth multiplier.
| Original language | English |
|---|---|
| Pages (from-to) | 1179-1180 |
| Journal | Electronics Letters |
| Volume | 34 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 11 Jun 1998 |
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