Modified booth pipelined multiplication
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Related Research Unit(s)
|Journal / Publication||Electronics Letters|
|Publication status||Published - 11 Jun 1998|
|Link to Scopus||https://www.scopus.com/record/display.uri?eid=2-s2.0-0032098859&origin=recordpage|
A pipelined modified Booth multiplication is proposed for low power, high performance DSP application. The proposed multiplication is suitable for VLSI implementation. It has a better power-performance ratio than the traditional pipelined multiplier and modified Booth multiplier.