Modelling of semiconductor wafer fabrication systems by extended object-oriented Petri nets
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
Author(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 471-495 |
| Journal / Publication | International Journal of Production Research |
| Volume | 43 |
| Issue number | 3 |
| Publication status | Published - 1 Feb 2005 |
Link(s)
Abstract
In this paper, extended object-oriented Petri nets (EOPNs) are proposed for the effective modelling of semiconductor wafer fabrication systems (SWFSs). To cope with their complexity in terms of the re-entrant process route and the mixed production mode, a special type of transition called main-bus gate is introduced, which may lead each kind of product to undergo every re-entrant processing stage. In addition, the hierarchical approach is also applied to cope with the complexity. An etching area that processes 0.25 μm logic IC products is taken as an illustration to present the detailed modelling procedures by EOPNs, and the resulting model validates that the EOPNs may cope well with complex SWFSs modelling. © 2005 Taylor & Francis Ltd.
Research Area(s)
- Extended object-oriented Petri nets (EOPNs), Main-bus gate (MBG), Modelling, Semiconductor wafer fabrication system (SWFS)
Citation Format(s)
Modelling of semiconductor wafer fabrication systems by extended object-oriented Petri nets. / Liu, Huiran; Fung, Richard Y. K.; Jiang, Zhibin.
In: International Journal of Production Research, Vol. 43, No. 3, 01.02.2005, p. 471-495.
In: International Journal of Production Research, Vol. 43, No. 3, 01.02.2005, p. 471-495.
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
