Modeling of the parasitic transistor-induced drain breakdown in MOSFET's

Hei Wong

doi:10.1109/16.544391

Author(s)

Hei Wong

Related Research Unit(s)

Department of Electrical Engineering

Detail(s)

Original language	English
Pages (from-to)	2190-2196
Journal / Publication	IEEE Transactions on Electron Devices
Volume	43
Issue number	12
Publication status	Published - 1996

Link(s)

DOI	DOI https://doi.org/10.1109/16.544391 Final Published version
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Link to Scopus	https://www.scopus.com/record/display.uri?eid=2-s2.0-0030410867&origin=recordpage
Permanent Link	https://scholars.cityu.edu.hk/en/publications/publication(ae158675-6e20-461f-bf01-669e11129f92).html

Abstract

Parasitic bipolar transistor (PBT) induced break-down characteristics in MOSFET's are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the break-down voltage for the PBT-induced breakdown can be increased by rising the temperature, increasing the channel length, and reducing the substrate resistance. © 1996 IEEE.

Citation Format(s)

[ RIS ] [ BibTeX ]

Modeling of the parasitic transistor-induced drain breakdown in MOSFET's. / Wong, Hei.
In: IEEE Transactions on Electron Devices, Vol. 43, No. 12, 1996, p. 2190-2196.

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

Wong, H 1996, 'Modeling of the parasitic transistor-induced drain breakdown in MOSFET's', IEEE Transactions on Electron Devices, vol. 43, no. 12, pp. 2190-2196. https://doi.org/10.1109/16.544391

Wong, H. (1996). Modeling of the parasitic transistor-induced drain breakdown in MOSFET's. IEEE Transactions on Electron Devices, 43(12), 2190-2196. https://doi.org/10.1109/16.544391

Wong H. Modeling of the parasitic transistor-induced drain breakdown in MOSFET's. IEEE Transactions on Electron Devices. 1996;43(12):2190-2196. doi: 10.1109/16.544391

Wong, Hei. / Modeling of the parasitic transistor-induced drain breakdown in MOSFET's. In: IEEE Transactions on Electron Devices. 1996 ; Vol. 43, No. 12. pp. 2190-2196.