Modeling of the parasitic transistor-induced drain breakdown in MOSFET's

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Pages (from-to)2190-2196
Journal / PublicationIEEE Transactions on Electron Devices
Volume43
Issue number12
Publication statusPublished - 1996

Abstract

Parasitic bipolar transistor (PBT) induced break-down characteristics in MOSFET's are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the break-down voltage for the PBT-induced breakdown can be increased by rising the temperature, increasing the channel length, and reducing the substrate resistance. © 1996 IEEE.