TY - GEN
T1 - Model Analysis of Electron Tunneling Through n-Type Silicon/Silicon Oxide Interfaces
AU - Filip, V.
AU - Wong, H.
AU - Chu, P. L.
PY - 2003/12
Y1 - 2003/12
N2 - Interfaces between n-type silicon and silicon oxide are investigated by comparing the experimental current-voltage characteristics with corresponding theoretical calculations. Two models, namely simple tunneling and tunneling surface quantum well models, are used for the calculations. According to the present results, even if the field penetration in Si may be significant, the contribution of the field-induced states is not essential in practical analysis for gate oxide thickness down to 2.1 nm.
AB - Interfaces between n-type silicon and silicon oxide are investigated by comparing the experimental current-voltage characteristics with corresponding theoretical calculations. Two models, namely simple tunneling and tunneling surface quantum well models, are used for the calculations. According to the present results, even if the field penetration in Si may be significant, the contribution of the field-induced states is not essential in practical analysis for gate oxide thickness down to 2.1 nm.
UR - https://www.scopus.com/pages/publications/84946405230
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84946405230&origin=recordpage
U2 - 10.1109/EDSSC.2003.1283548
DO - 10.1109/EDSSC.2003.1283548
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 0-7803-7749-4
T3 - IEEE Conference on Electron Devices and Solid-State Circuits
SP - 353
EP - 356
BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits
PB - IEEE
T2 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits
Y2 - 16 December 2003 through 18 December 2003
ER -