TY - GEN
T1 - Material and interface instabilities of hafnium gate oxide
AU - Wong, Hei
PY - 2004
Y1 - 2004
N2 - The silicon technology will continue its historical rate of advancement with the Moore's law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit. Introducing a physical thicker high-κ dielectric film, such as hafnium oxide, can overcome this constraint. However, high-κ gate dielectric film still gives rise to several reliability problems. This paper reviews the recent report on the material and interface instabilities of using hafnium oxide as the MOS gate dielectric. It is found that the hafnium oxide is thermal unstable because of the decomposition of more ionic Hf-O bond and the low crystallization temperature. On the other, hand, the interface trap density of HfO2/Si interface is very high (∼ 1012 cm -2) because of the presence of Hf-Si bonds. Yet silicon oxide/high-κ or oxynitride/high-κ stack could be a short-term solution for the emerging nanometer gate length technology. © 2004 IEEE.
AB - The silicon technology will continue its historical rate of advancement with the Moore's law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit. Introducing a physical thicker high-κ dielectric film, such as hafnium oxide, can overcome this constraint. However, high-κ gate dielectric film still gives rise to several reliability problems. This paper reviews the recent report on the material and interface instabilities of using hafnium oxide as the MOS gate dielectric. It is found that the hafnium oxide is thermal unstable because of the decomposition of more ionic Hf-O bond and the low crystallization temperature. On the other, hand, the interface trap density of HfO2/Si interface is very high (∼ 1012 cm -2) because of the presence of Hf-Si bonds. Yet silicon oxide/high-κ or oxynitride/high-κ stack could be a short-term solution for the emerging nanometer gate length technology. © 2004 IEEE.
UR - https://www.scopus.com/pages/publications/21644444997
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-21644444997&origin=recordpage
M3 - RGC 32 - Refereed conference paper (with host publication)
VL - 1
SP - 378
EP - 383
BT - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
T2 - 7th International Conference on Solid-State and Integrated Circuits Technology (ICSICT 2004)
Y2 - 18 October 2004 through 21 October 2004
ER -