Low-cost memory data scheduling method for reconfigurable FFT bit-reversal circuits

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

3 Scopus Citations
View graph of relations

Author(s)

Related Research Unit(s)

Detail(s)

Original languageEnglish
Pages (from-to)217-219
Journal / PublicationElectronics Letters
Volume51
Issue number3
Publication statusPublished - 5 Feb 2015

Abstract

A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.