Low power probabilistic floating point multiplier design

Aman Gupta; Satyam Mandavalli; Vincent J. Mooney; Keck-Voon Ling; Arindam Basu; Henry Johan; Budianto Tandianus

doi:10.1109/ISVLSI.2011.54

Low power probabilistic floating point multiplier design

Aman Gupta
, Satyam Mandavalli
, Vincent J. Mooney
, Keck-Voon Ling
, Arindam Basu
, Henry Johan
, Budianto Tandianus

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

29 Citations (Scopus)

Abstract

We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image. © 2011 IEEE.

Original language	English
Title of host publication	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages	182-187
DOIs	https://doi.org/10.1109/ISVLSI.2011.54
Publication status	Published - 2011
Externally published	Yes
Event	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India Duration: 4 Jul 2011 → 6 Jul 2011

Publication series

Name	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Conference

Conference	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Place	India
City	Chennai
Period	4/07/11 → 6/07/11

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Research Keywords

Floating point multiplication
Probabilistic computation

Access Output

10.1109/ISVLSI.2011.54

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Gupta, A., Mandavalli, S., Mooney, V. J., Ling, K.-V., Basu, A., Johan, H., & Tandianus, B. (2011). Low power probabilistic floating point multiplier design. In Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 (pp. 182-187). Article 5992502 (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011). https://doi.org/10.1109/ISVLSI.2011.54

@inproceedings{de698cae23f449c3af8c35cdc26f3b8d,

title = "Low power probabilistic floating point multiplier design",

abstract = "We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31\% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image. {\textcopyright} 2011 IEEE.",

keywords = "Floating point multiplication, Probabilistic computation",

author = "Aman Gupta and Satyam Mandavalli and Mooney, \{Vincent J.\} and Keck-Voon Ling and Arindam Basu and Henry Johan and Budianto Tandianus",

note = "Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].; 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 ; Conference date: 04-07-2011 Through 06-07-2011",

year = "2011",

doi = "10.1109/ISVLSI.2011.54",

language = "English",

isbn = "9780769544472",

series = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

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booktitle = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

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Gupta, A, Mandavalli, S, Mooney, VJ, Ling, K-V, Basu, A, Johan, H & Tandianus, B 2011, Low power probabilistic floating point multiplier design. in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011., 5992502, Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, pp. 182-187, 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, India, 4/07/11. https://doi.org/10.1109/ISVLSI.2011.54

Low power probabilistic floating point multiplier design. / Gupta, Aman; Mandavalli, Satyam; Mooney, Vincent J. et al.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. 2011. p. 182-187 5992502 (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Low power probabilistic floating point multiplier design

AU - Gupta, Aman

AU - Mandavalli, Satyam

AU - Mooney, Vincent J.

AU - Ling, Keck-Voon

AU - Basu, Arindam

AU - Johan, Henry

AU - Tandianus, Budianto

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

PY - 2011

Y1 - 2011

N2 - We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image. © 2011 IEEE.

AB - We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image. © 2011 IEEE.

KW - Floating point multiplication

KW - Probabilistic computation

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U2 - 10.1109/ISVLSI.2011.54

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M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9780769544472

T3 - Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

SP - 182

EP - 187

BT - Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

T2 - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Y2 - 4 July 2011 through 6 July 2011

ER -

Low power probabilistic floating point multiplier design

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

Research Keywords

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