Low Power Pre-comparison Configuration Strategy for a Logic-based Binary CAM on FPGA

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)

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Detail(s)

Original languageEnglish
Title of host publication2019 Second International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT)
PublisherIEEE
ISBN (Electronic)978-1-7281-2435-3
Publication statusPublished - Nov 2019

Publication series

Name2nd International Conference on Latest Trends in Electrical Engineering and Computing Technologies, INTELLECT

Conference

Title2nd International Conference on Latest Trends in Electrical Engineering and Computing Technologies, INTELLECT 2019
PlacePakistan
CityKarachi
Period13 - 14 November 2019

Abstract

Content-addressable memory (CAM) is considered an efficient searching technology due to the fact that the output is processed in a deterministic time. However, traditional CAM cannot be implemented on field-programmable gate array (FPGA) owing to the lack of architectural support. Thus, researchers use FPGA resources, i.e., random-access memory, lookup tables, and slice registers to emulate CAM. Unfortunately, FPGA-based CAMs have higher power consumption owing to the concurrent activation of the entire CAM components. Therefore, it is indispensable to design such a strategy that can activate merely the required resources and ultimately reduce the power consumption. In this paper, we present a pre-comparison configuration strategy on a logic-based binary CAM. The proposed CAM has two segments such that the first segment when matched with a few bits of the search key enables the second segment. Thus, it results in power reduction during a search operation. A sample of 64 × 36 of the proposed CAM is implemented on a Xilinx Virtex-6 FPGA. Implementation results show a reduction of 31.27% in power consumption when compared to the latest FPGA-based CAMs without sacrificing the throughput.

Research Area(s)

  • Binary CAM, FPGA, FPGA-based CAM, Logic-based CAM, Power reduction, Pre-comparison strategy, Traditional CAM

Citation Format(s)

Low Power Pre-comparison Configuration Strategy for a Logic-based Binary CAM on FPGA. / Rehman, Najib Ur; Mujahid, Omer; Irfan, Muhammad; Hafeez, Abdul; Ullah, Zahid.

2019 Second International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT). IEEE, 2019. 8955476 (2nd International Conference on Latest Trends in Electrical Engineering and Computing Technologies, INTELLECT).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)