TY - GEN
T1 - Low power low voltage adder for high performance DSP
AU - Wu, Angus
AU - Ng, C. K.
PY - 1997
Y1 - 1997
N2 - A high performance low voltage adder has been designed. The proposed circuit has better circuit performances in terms of power consumption and area efficiency comparing to the conventional CMOS logic, the energy efficient Double Pass Transistor logic, Complementary Pass Transistor logic, Transmission Gate logic, Swing Restored Pass-Transistor logic, and recently developed Complementary Pass Transistor-Transmission Gate logic. The proposed low power adder is used to implement high performance pipelined multiplier.
AB - A high performance low voltage adder has been designed. The proposed circuit has better circuit performances in terms of power consumption and area efficiency comparing to the conventional CMOS logic, the energy efficient Double Pass Transistor logic, Complementary Pass Transistor logic, Transmission Gate logic, Swing Restored Pass-Transistor logic, and recently developed Complementary Pass Transistor-Transmission Gate logic. The proposed low power adder is used to implement high performance pipelined multiplier.
UR - http://www.scopus.com/inward/record.url?scp=1842779875&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-1842779875&origin=recordpage
M3 - RGC 32 - Refereed conference paper (with host publication)
VL - 7
SP - 541
EP - 544
BT - International Symposium on IC Technology, Systems and Applications
T2 - 7th International Symposium on IC Technology, Systems and Applications ISIC 97
Y2 - 10 September 1997 through 12 September 1997
ER -