TY - JOUR
T1 - Low-cost memory data scheduling method for reconfigurable FFT bit-reversal circuits
AU - Gao, Wei
AU - Kwong, Sam
AU - Sang, Hongshi
PY - 2015/2/5
Y1 - 2015/2/5
N2 - A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.
AB - A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.
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U2 - 10.1049/el.2014.3715
DO - 10.1049/el.2014.3715
M3 - RGC 21 - Publication in refereed journal
SN - 0013-5194
VL - 51
SP - 217
EP - 219
JO - Electronics Letters
JF - Electronics Letters
IS - 3
ER -