Low cost meander line chip monopole antenna

Mike W. K. Lee; K. W. Leung; Y. L. Chow

doi:10.1109/TAP.2013.2287518

Low cost meander line chip monopole antenna

Mike W. K. Lee, K. W. Leung, Y. L. Chow

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

23 Citations (Scopus)

Abstract

A method for miniaturizing a chip antenna is presented in this communication. It uses a folded meander line and therefore the length is half. Also, two upper and lower loading patches are used to improve the performance of the chip antenna. The chip antenna has been miniaturized to 3.2 × 1.6 × 0.83 mm³ at resonance measured frequencies of 2.45 GHz and 2.73 GHz with and without external matching, respectively. An economic fabrication method for the chip antenna is discussed. It uses an inexpensive multilayer PCB with two low-cost prepregs and a common laminate. Only two plated-through holes are needed for the whole design. Good agreement between the simulated and measured results is observed. © 2013 IEEE.

Original language	English
Article number	6648649
Pages (from-to)	442-445
Journal	IEEE Transactions on Antennas and Propagation
Volume	62
Issue number	1
DOIs	https://doi.org/10.1109/TAP.2013.2287518
Publication status	Published - Jan 2014

Research Keywords

Chip antenna
core
loading patch
meander line antenna
prepreg

Access Output

10.1109/TAP.2013.2287518

Other Access Options

Check CityUHK Library

Permanent Link

Right click to copy link

Cite this

@article{cc13bc0e689a4cee9e403330f1455c10,

title = "Low cost meander line chip monopole antenna",

abstract = "A method for miniaturizing a chip antenna is presented in this communication. It uses a folded meander line and therefore the length is half. Also, two upper and lower loading patches are used to improve the performance of the chip antenna. The chip antenna has been miniaturized to 3.2 × 1.6 × 0.83 mm3 at resonance measured frequencies of 2.45 GHz and 2.73 GHz with and without external matching, respectively. An economic fabrication method for the chip antenna is discussed. It uses an inexpensive multilayer PCB with two low-cost prepregs and a common laminate. Only two plated-through holes are needed for the whole design. Good agreement between the simulated and measured results is observed. {\textcopyright} 2013 IEEE.",

keywords = "Chip antenna, core, loading patch, meander line antenna, prepreg",

author = "Lee, {Mike W. K.} and Leung, {K. W.} and Chow, {Y. L.}",

year = "2014",

month = jan,

doi = "10.1109/TAP.2013.2287518",

language = "English",

volume = "62",

pages = "442--445",

journal = "IEEE Transactions on Antennas and Propagation",

issn = "0018-926X",

publisher = "IEEE",

number = "1",

}

TY - JOUR

T1 - Low cost meander line chip monopole antenna

AU - Lee, Mike W. K.

AU - Leung, K. W.

AU - Chow, Y. L.

PY - 2014/1

Y1 - 2014/1

N2 - A method for miniaturizing a chip antenna is presented in this communication. It uses a folded meander line and therefore the length is half. Also, two upper and lower loading patches are used to improve the performance of the chip antenna. The chip antenna has been miniaturized to 3.2 × 1.6 × 0.83 mm3 at resonance measured frequencies of 2.45 GHz and 2.73 GHz with and without external matching, respectively. An economic fabrication method for the chip antenna is discussed. It uses an inexpensive multilayer PCB with two low-cost prepregs and a common laminate. Only two plated-through holes are needed for the whole design. Good agreement between the simulated and measured results is observed. © 2013 IEEE.

AB - A method for miniaturizing a chip antenna is presented in this communication. It uses a folded meander line and therefore the length is half. Also, two upper and lower loading patches are used to improve the performance of the chip antenna. The chip antenna has been miniaturized to 3.2 × 1.6 × 0.83 mm3 at resonance measured frequencies of 2.45 GHz and 2.73 GHz with and without external matching, respectively. An economic fabrication method for the chip antenna is discussed. It uses an inexpensive multilayer PCB with two low-cost prepregs and a common laminate. Only two plated-through holes are needed for the whole design. Good agreement between the simulated and measured results is observed. © 2013 IEEE.

KW - Chip antenna

KW - core

KW - loading patch

KW - meander line antenna

KW - prepreg

UR - http://www.scopus.com/inward/record.url?scp=84892517370&partnerID=8YFLogxK

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84892517370&origin=recordpage

U2 - 10.1109/TAP.2013.2287518

DO - 10.1109/TAP.2013.2287518

M3 - RGC 21 - Publication in refereed journal

SN - 0018-926X

VL - 62

SP - 442

EP - 445

JO - IEEE Transactions on Antennas and Propagation

JF - IEEE Transactions on Antennas and Propagation

IS - 1

M1 - 6648649

ER -

Low cost meander line chip monopole antenna

Abstract

Research Keywords

Access Output

Other Access Options

Permanent Link

Other Files and Links

Fingerprint

Cite this