LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY

Meikang Qiu; Jiande Wu; Chun Jason Xue; Jingtong Aaron Hu; Wei-Che Tseng; Edwin H.-M. Sha

doi:10.1109/FPL.2008.4629983

LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY

Meikang Qiu
, Jiande Wu
, Chun Jason Xue
, Jingtong Aaron Hu
, Wei-Che Tseng
, Edwin H.-M. Sha

Department of Computer Science

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

2 Citations (Scopus)

Abstract

Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU. ©2008 IEEE.

Original language	English
Title of host publication	Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Pages	459-462
DOIs	https://doi.org/10.1109/FPL.2008.4629983
Publication status	Published - Sept 2008
Event	2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany Duration: 8 Sept 2008 → 10 Sept 2008

Conference

Conference	2008 International Conference on Field Programmable Logic and Applications, FPL
Place	Germany
City	Heidelberg
Period	8/09/08 → 10/09/08

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@inproceedings{ba6f13f2f0c44d07aab70b0330fbce0f,

title = "LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY",

abstract = "Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU. {\textcopyright}2008 IEEE.",

author = "Meikang Qiu and Jiande Wu and Xue, \{Chun Jason\} and Hu, \{Jingtong Aaron\} and Wei-Che Tseng and Sha, \{Edwin H.-M.\}",

year = "2008",

month = sep,

doi = "10.1109/FPL.2008.4629983",

language = "English",

isbn = "978-1-4244-1960-9",

pages = "459--462",

booktitle = "Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL",

note = "2008 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 08-09-2008 Through 10-09-2008",

}

Qiu, M, Wu, J, Xue, CJ, Hu, JA, Tseng, W-C & Sha, EH-M 2008, LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY. in Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL., 4629983, pp. 459-462, 2008 International Conference on Field Programmable Logic and Applications, FPL, Heidelberg, Germany, 8/09/08. https://doi.org/10.1109/FPL.2008.4629983

LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY. / Qiu, Meikang; Wu, Jiande; Xue, Chun Jason et al.
Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 459-462 4629983.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY

AU - Qiu, Meikang

AU - Wu, Jiande

AU - Xue, Chun Jason

AU - Hu, Jingtong Aaron

AU - Tseng, Wei-Che

AU - Sha, Edwin H.-M.

PY - 2008/9

Y1 - 2008/9

N2 - Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU. ©2008 IEEE.

AB - Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU. ©2008 IEEE.

UR - https://www.scopus.com/pages/publications/54949135289

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-54949135289&origin=recordpage

U2 - 10.1109/FPL.2008.4629983

DO - 10.1109/FPL.2008.4629983

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 978-1-4244-1960-9

SP - 459

EP - 462

BT - Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

T2 - 2008 International Conference on Field Programmable Logic and Applications, FPL

Y2 - 8 September 2008 through 10 September 2008

ER -

LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY

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