TY - GEN
T1 - Lightweight secure processor prototype on FPGA
AU - Liu, Yao
AU - Cheung, Ray C.C.
AU - Wong, Hei
N1 - Full text of this publication does not contain sufficient affiliation information. With consent from the author(s) concerned, the Research Unit(s) information for this record is based on the existing academic department affiliation of the author(s).
PY - 2018/8
Y1 - 2018/8
N2 - Lightweight devices usually come with an additional cryptographic co-processor for enabling the secrecy, in contrast, the master processor is typically a commercial processor where the required protection mechanism is missing. In this paper, an on-going effort in secured architecture named S-RISC-V based on RISC-V core is introduced. The mechanism of key generation used for memory protection is supported together with the joint efforts in the following perspectives, including ISA extension, compiler improvement, and hardware implementation. The architecture has been verified on Zedboard running at 25MHz, driven by the host ARM core. The area overhead is less than 10%, compared with the original RISC-V core.
AB - Lightweight devices usually come with an additional cryptographic co-processor for enabling the secrecy, in contrast, the master processor is typically a commercial processor where the required protection mechanism is missing. In this paper, an on-going effort in secured architecture named S-RISC-V based on RISC-V core is introduced. The mechanism of key generation used for memory protection is supported together with the joint efforts in the following perspectives, including ISA extension, compiler improvement, and hardware implementation. The architecture has been verified on Zedboard running at 25MHz, driven by the host ARM core. The area overhead is less than 10%, compared with the original RISC-V core.
KW - key generation
KW - RISC-V
KW - secure processor
UR - http://www.scopus.com/inward/record.url?scp=85060300425&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85060300425&origin=recordpage
U2 - 10.1109/FPL.2018.00081
DO - 10.1109/FPL.2018.00081
M3 - RGC 32 - Refereed conference paper (with host publication)
T3 - Proceedings - International Conference on Field-Programmable Logic and Applications, FPL
SP - 443
EP - 444
BT - Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
PB - IEEE
T2 - 28th International Conference on Field-Programmable Logic and Applications, FPL 2018
Y2 - 26 August 2018 through 30 August 2018
ER -