Lightweight secure processor prototype on FPGA

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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Detail(s)

Original languageEnglish
Title of host publicationProceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
PublisherIEEE
Pages443-444
ISBN (Electronic)978-1-5386-8517-4
Publication statusPublished - Aug 2018

Publication series

NameProceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018

Conference

Title28th International Conference on Field-Programmable Logic and Applications, FPL 2018
PlaceIreland
CityDublin
Period26 - 30 August 2018

Abstract

Lightweight devices usually come with an additional cryptographic co-processor for enabling the secrecy, in contrast, the master processor is typically a commercial processor where the required protection mechanism is missing. In this paper, an on-going effort in secured architecture named S-RISC-V based on RISC-V core is introduced. The mechanism of key generation used for memory protection is supported together with the joint efforts in the following perspectives, including ISA extension, compiler improvement, and hardware implementation. The architecture has been verified on Zedboard running at 25MHz, driven by the host ARM core. The area overhead is less than 10%, compared with the original RISC-V core.

Research Area(s)

  • key generation, RISC-V, secure processor

Bibliographic Note

Full text of this publication does not contain sufficient affiliation information. With consent from the author(s) concerned, the Research Unit(s) information for this record is based on the existing academic department affiliation of the author(s).

Citation Format(s)

Lightweight secure processor prototype on FPGA. / Liu, Yao; Cheung, Ray C.C.; Wong, Hei.

Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. IEEE, 2018. p. 443-444 8530789 (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review