Abstract
With the increasing bit density and adoption of 3D NAND, flash memory suffers from increased errors. To address the issue, flash devices adopt error correction codes (ECC) with strong error correction capability, like low-density parity-check (LDPC) code, to correct errors. The drawback of LDPC is that, to correct data with a high raw bit error rate (RBER), read latency will be amplified. This work proposes to address this issue with the assistance of approximate data. First, studies have been conducted and show there are ample amount of approximate data available in flash storage. Second, a novel data organization is proposed to fortify the reliability of regular data by leaving approximate data unprotected. Finally, a new data allocation strategy and modified garbage collection scheme are presented to complete the design. The experimental results show that the proposed approach can improve read performance by 30% on average comparing to current techniques.
| Original language | English |
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| Title of host publication | Proceedings of the 56th Annual Design Automation Conference 2019 |
| Publisher | Association for Computing Machinery |
| ISBN (Electronic) | 978-1-4503-6725-7 |
| DOIs | |
| Publication status | Published - 6 Jun 2019 |
| Event | 56th Design Automation Conference (DAC 2019) - Las Vegas Convention Center., Las Vegas, United States Duration: 2 Jun 2019 → 6 Jun 2019 https://www.dac.com/ |
Publication series
| Name | Proceedings - Design Automation Conference |
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| ISSN (Print) | 0738-100X |
Conference
| Conference | 56th Design Automation Conference (DAC 2019) |
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| Place | United States |
| City | Las Vegas |
| Period | 2/06/19 → 6/06/19 |
| Internet address |