Layer-by-layer-assembled reduced graphene oxide/gold nanoparticle hybrid double-floating-gate structure for low-voltage flexible flash memory

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

170 Scopus Citations
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Author(s)

  • Su-Ting Han
  • Ye Zhou
  • Chundong Wang
  • Lifang He

Detail(s)

Original languageEnglish
Pages (from-to)872-877
Journal / PublicationAdvanced Materials
Volume25
Issue number6
Publication statusPublished - 13 Feb 2013

Abstract

A hybrid double-floating-gate flexible memory device by utilizing an rGO-sheet monolayer and a Au NP array as upper and lower floating gates is reported. The rGO buffer layer acts as a charge-trapping layer and introduces an energy barrier between the Au NP lower floating gate and the channel. The proposed memory device demonstrates a strong improvement in both field-effect-transistor (FET) and memory characteristics. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Research Area(s)

  • flexible flash memory, gold nanoparticles, hybrid double floating gates, low voltage, reduced graphene oxide

Citation Format(s)