Lanthana and its interface with silicon

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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Detail(s)

Original languageEnglish
Title of host publicationProceedings of the International Conference on Microelectronics, ICM
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages35-41
ISBN (Print)9781479952960
Publication statusPublished - 2014

Conference

Title2014 29th International Conference on Microelectronics, MIEL 2014
PlaceSerbia
CityBelgrade
Period12 - 14 May 2014

Abstract

In couple of years, the CMOS devices will be scaled down to the decananometer range and the gate dielectric thickness, in the sense of oxide equivalent thickness (EOT), will be shrunk into the subnanometer scale. A higher dielectric constant material must be introduced. Lanthanum oxide or lanthana has been considered to be one of the promising next generation gate dielectric materials. However, it was found that when lanthana is brought into contact with the silicon substrate, several undesirable effects, leading to significant device characteristic degradations, occur. In this review, some issues related to the material interaction at the lanthana/Si interface will be discussed. Some measures for overcoming the adverse effects of lanthana film, such as chemical doping and oxygen chemical potential control, will be highlighted. © 2014 IEEE.

Citation Format(s)

Lanthana and its interface with silicon. / Wong, Hei.

Proceedings of the International Conference on Microelectronics, ICM. Institute of Electrical and Electronics Engineers Inc., 2014. p. 35-41 6842082.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review