In couple of years, the CMOS devices will be scaled down to the decananometer range and the gate dielectric thickness, in the sense of oxide equivalent thickness (EOT), will be shrunk into the subnanometer scale. A higher dielectric constant material must be introduced. Lanthanum oxide or lanthana has been considered to be one of the promising next generation gate dielectric materials. However, it was found that when lanthana is brought into contact with the silicon substrate, several undesirable effects, leading to significant device characteristic degradations, occur. In this review, some issues related to the material interaction at the lanthana/Si interface will be discussed. Some measures for overcoming the adverse effects of lanthana film, such as chemical doping and oxygen chemical potential control, will be highlighted. © 2014 IEEE.