Joint profit and process variation aware high level synthesis with speed binning

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Detail(s)

Original languageEnglish
Article number6893057
Pages (from-to)1640-1650
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number9
Publication statusPublished - 1 Sep 2015

Abstract

As integrated circuits continuously scale up, process variation plays an increasingly significant role in system design and semiconductor economic return. In this paper, we explore the potential of profit improvement under the inherent semiconductor variability based on the speed binning technique. We aim to develop a set of high level synthesis (HLS) solutions, for which purpose heuristic techniques, including allocation, scheduling, and resource binding, are proposed. The goal is to construct designs that maximize the number of chips that can be sold at the most advantageous price, leading to the maximization of the overall profit. In addition, a genetic algorithm-based formulation is constructed for HLS solutions. Then, we complement the HLS techniques with near-optimal bin placement strategies for further profit improvement. Experimental results confirm the superiority of the HLS results and the associated improvement in profit margins.

Research Area(s)

  • Embedded system, high level synthesis (HLS), process variation, profit, speed binning