Joint Management of CPU and NVDIMM for Breaking down the Great Memory Wall

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

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Author(s)

Detail(s)

Original languageEnglish
Article number8950228
Pages (from-to)722-733
Journal / PublicationIEEE Transactions on Computers
Volume69
Issue number5
Online published6 Jan 2020
Publication statusPublished - May 2020

Abstract

To provide larger memory space with lower costs, NVDIMM is a production-ready device. However, directly placing NVDIMM as the main memory would seriously degrade the system performance because of the "great memory wall" caused by the fact that in NVDIMM, the slow memory (e.g., flash memory) is several orders of magnitude slower than the fast memory (e.g., DRAM). In this article, we present a joint management framework of host/CPU and NVDIMM to break down the great memory wall by bridging the process information gap between host/CPU and NVDIMM. In this framework, a page semantic-aware strategy is proposed to precisely predict, mark, and relocate data or memory pages to the fast memory in advance by exploiting the process access patterns, so that the frequency of the slow memory accesses can be further reduced. The proposed framework with the proposed strategy was evaluated with several well-known benchmarks and the results are encouraging.

Research Area(s)

  • Deep learning, high performance computing (HPC), hybrid memory, large memory capacity, memory wall, NVDIMM, process access behaviors, process state diagram, response time

Citation Format(s)

Joint Management of CPU and NVDIMM for Breaking down the Great Memory Wall. / Wu, Chun-Feng; Chang, Yuan-Hao; Yang, Ming-Chang; Kuo, Tei-Wei.

In: IEEE Transactions on Computers, Vol. 69, No. 5, 8950228, 05.2020, p. 722-733.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal