I/O Scheduling with Mapping Cache Awareness for Flash Based Storage Systems

Cheng Ji, Chao Wu, Li-Pin Chang, Liang Shi*, Chun Jason Xue

*Corresponding author for this work

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

1 Citation (Scopus)

Abstract

NAND ash memory has been the default storage component in mobile systems. One of the key technologies for ash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in ash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of mobile storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles: Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Experimental results show that MAP improved upon traditional I/O schedulers by 30% and 8% in terms of read and write latencies, respectively.
Original languageEnglish
Title of host publicationProceedings of the 13th International Conference on Embedded Software, EMSOFT 2016
PublisherAssociation for Computing Machinery
ISBN (Print)9781450344852
DOIs
Publication statusPublished - Oct 2016
Event13th International Conference on Embedded Software (EMSOFT '16) - Pittsburgh, United States
Duration: 1 Oct 20167 Oct 2016

Conference

Conference13th International Conference on Embedded Software (EMSOFT '16)
PlaceUnited States
CityPittsburgh
Period1/10/167/10/16

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