Interconnecting multiple input and output LAN-s over a high speed gateway

Imrich Chlamtac; Eric W M Wong

Interconnecting multiple input and output LAN-s over a high speed gateway

Imrich Chlamtac
, Eric W M Wong

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

The control and buffer assignment of a gateway interconnecting multiple LAN-s has been so far rigorously studied only for a single output LAN. In this paper we consider a more realistic multiple input and multiple output LAN-s interconnection. We derive an optimal method for controlling traffic flow to minimize packet loss, given a finite buffers space at each LAN. We also show that the optimal buffer allocation among the input and the output buffers depends on the relative number of the interconnected input and output LAN-s. A new approximate analytic model is provided which is shown to be tractable while introducing only small errors.

Original language	English
Title of host publication	Proceedings of the 1993 IEEE International Conference on Communications
Publisher	IEEE
Pages	37-41
ISBN (Print)	780309510
Publication status	Published - 1993
Externally published	Yes
Event	Proceedings of the IEEE International Conference on Communications '93 - Geneva, Switz Duration: 23 May 1993 → 26 May 1993

Conference

Conference	Proceedings of the IEEE International Conference on Communications '93
City	Geneva, Switz
Period	23/05/93 → 26/05/93

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title = "Interconnecting multiple input and output LAN-s over a high speed gateway",

abstract = "The control and buffer assignment of a gateway interconnecting multiple LAN-s has been so far rigorously studied only for a single output LAN. In this paper we consider a more realistic multiple input and multiple output LAN-s interconnection. We derive an optimal method for controlling traffic flow to minimize packet loss, given a finite buffers space at each LAN. We also show that the optimal buffer allocation among the input and the output buffers depends on the relative number of the interconnected input and output LAN-s. A new approximate analytic model is provided which is shown to be tractable while introducing only small errors.",

author = "Imrich Chlamtac and Wong, \{Eric W M\}",

year = "1993",

language = "English",

isbn = "780309510",

pages = "37--41",

booktitle = "Proceedings of the 1993 IEEE International Conference on Communications",

publisher = "IEEE",

address = "United States",

note = "Proceedings of the IEEE International Conference on Communications '93 ; Conference date: 23-05-1993 Through 26-05-1993",

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T1 - Interconnecting multiple input and output LAN-s over a high speed gateway

AU - Chlamtac, Imrich

AU - Wong, Eric W M

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Y1 - 1993

N2 - The control and buffer assignment of a gateway interconnecting multiple LAN-s has been so far rigorously studied only for a single output LAN. In this paper we consider a more realistic multiple input and multiple output LAN-s interconnection. We derive an optimal method for controlling traffic flow to minimize packet loss, given a finite buffers space at each LAN. We also show that the optimal buffer allocation among the input and the output buffers depends on the relative number of the interconnected input and output LAN-s. A new approximate analytic model is provided which is shown to be tractable while introducing only small errors.

AB - The control and buffer assignment of a gateway interconnecting multiple LAN-s has been so far rigorously studied only for a single output LAN. In this paper we consider a more realistic multiple input and multiple output LAN-s interconnection. We derive an optimal method for controlling traffic flow to minimize packet loss, given a finite buffers space at each LAN. We also show that the optimal buffer allocation among the input and the output buffers depends on the relative number of the interconnected input and output LAN-s. A new approximate analytic model is provided which is shown to be tractable while introducing only small errors.

UR - https://www.scopus.com/pages/publications/0027149689

UR - https://www.scopus.com/pages/publications/0027149689#tab=impact

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 780309510

SP - 37

EP - 41

BT - Proceedings of the 1993 IEEE International Conference on Communications

PB - IEEE

T2 - Proceedings of the IEEE International Conference on Communications '93

Y2 - 23 May 1993 through 26 May 1993

ER -

Interconnecting multiple input and output LAN-s over a high speed gateway

Abstract

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