Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

Jie Zhou; Youshu Ji; Ning Wang; Yuchen Hu; Xinyao Jiao; Bingkun Yao; Xinwei Fang; Shuai Zhao; Nan Guan; Zhe Jiang

doi:10.1109/DAC63849.2025.11133100

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

Jie Zhou
, Youshu Ji
, Ning Wang
, Yuchen Hu
, Xinyao Jiao
, Bingkun Yao
, Xinwei Fang^*
, Shuai Zhao^*
, Nan Guan
, Zhe Jiang^*

^*Corresponding author for this work

Department of Computer Science

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

1 Citation (Scopus)

Abstract

SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1-preview by up to 11.97%. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25. © 2025 IEEE.

Original language	English
Title of host publication	2025 62nd ACM/IEEE Design Automation Conference (DAC)
Publisher	IEEE
Number of pages	7
ISBN (Electronic)	9798331503048
ISBN (Print)	979-8-3315-0305-5
DOIs	https://doi.org/10.1109/DAC63849.2025.11133100
Publication status	Published - 2025
Event	62nd ACM/IEEE Design Automation Conference (DAC 2025) - San Francisco, United States Duration: 22 Jun 2025 → 25 Jun 2025

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	62nd ACM/IEEE Design Automation Conference (DAC 2025)
Place	United States
City	San Francisco
Period	22/06/25 → 25/06/25

Funding

We appreciate the reviewers for their helpful feedback. This work is supported by the National Key Research and Development Program (Grant No. 2024YFB4405600), the National Natural Science Foundation of China (Grant No. 62472086), the Basic Research Program of Jiangsu (Grant No. BK20243042), the Science and Technology Major Special Program of Jiangsu (No. BG2024010), and the Start-up Research Fund of Southeast University (Grant No. RF1028624005).

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10.1109/DAC63849.2025.11133100

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@inproceedings{17ba02d44917438aaf8b7b98b25a2c93,

title = "Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design",

abstract = "SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54\% on our testbench, significantly outperforming OpenAI's o1-preview by up to 11.97\%. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25. {\textcopyright} 2025 IEEE.",

author = "Jie Zhou and Youshu Ji and Ning Wang and Yuchen Hu and Xinyao Jiao and Bingkun Yao and Xinwei Fang and Shuai Zhao and Nan Guan and Zhe Jiang",

year = "2025",

doi = "10.1109/DAC63849.2025.11133100",

language = "English",

isbn = "979-8-3315-0305-5",

series = "Proceedings - Design Automation Conference",

publisher = "IEEE",

booktitle = "2025 62nd ACM/IEEE Design Automation Conference (DAC)",

address = "United States",

note = "62nd ACM/IEEE Design Automation Conference (DAC 2025) ; Conference date: 22-06-2025 Through 25-06-2025",

}

Zhou, J, Ji, Y, Wang, N, Hu, Y, Jiao, X, Yao, B, Fang, X, Zhao, S, Guan, N & Jiang, Z 2025, Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. in 2025 62nd ACM/IEEE Design Automation Conference (DAC). Proceedings - Design Automation Conference, IEEE, 62nd ACM/IEEE Design Automation Conference (DAC 2025), San Francisco, California, United States, 22/06/25. https://doi.org/10.1109/DAC63849.2025.11133100

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. / Zhou, Jie; Ji, Youshu; Wang, Ning et al.
2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025. (Proceedings - Design Automation Conference).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

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T2 - 62nd ACM/IEEE Design Automation Conference (DAC 2025)

AU - Zhou, Jie

AU - Ji, Youshu

AU - Wang, Ning

AU - Hu, Yuchen

AU - Jiao, Xinyao

AU - Yao, Bingkun

AU - Fang, Xinwei

AU - Zhao, Shuai

AU - Guan, Nan

AU - Jiang, Zhe

PY - 2025

Y1 - 2025

N2 - SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1-preview by up to 11.97%. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25. © 2025 IEEE.

AB - SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1-preview by up to 11.97%. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25. © 2025 IEEE.

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M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 979-8-3315-0305-5

T3 - Proceedings - Design Automation Conference

BT - 2025 62nd ACM/IEEE Design Automation Conference (DAC)

PB - IEEE

Y2 - 22 June 2025 through 25 June 2025

ER -

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

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