Abstract
Motivated by the strong demand for flash memory with enhanced reliability, this work attempts to achieve improved flash-memory endurance without substantially increasing overhead and without excessively modifying popular implementation designs such as the Flash Translation Layer protocol (FTL), NAND Flash Translation Layer protocol (NFTL), and Block-Level flash translation layer protocol (BL). A wear-leveling mechanism for moving data that are not updated is proposed to distribute wear-leveling actions over the entire physical address space, so that static or rarely updated data can be proactively moved and memory-space requirements can be minimized. The properties of the mechanism are then explored with various implementation considerations. A series of experiments based on a realistic trace demonstrates the significantly improved endurance of FTL, NFTL, and BL with limited system overhead.
| Original language | English |
|---|---|
| Pages (from-to) | 53-65 |
| Journal | IEEE Transactions on Computers |
| Volume | 59 |
| Issue number | 1 |
| Online published | 10 Sept 2009 |
| DOIs | |
| Publication status | Published - Jan 2010 |
| Externally published | Yes |
Research Keywords
- Endurance
- Flash memory
- Reliability
- Wear leveling
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