High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

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Author(s)

  • Yuan Liu
  • Jiming Sheng
  • Hao Wu
  • Hung-Chieh Cheng
  • Muhammad Imran Shakir
  • Yu Huang
  • Xiangfeng Duan

Detail(s)

Original languageEnglish
Pages (from-to)4120-4125
Journal / PublicationAdvanced Materials
Volume28
Issue number21
Online published1 Apr 2016
Publication statusPublished - 1 Jun 2016
Externally publishedYes

Abstract

Scalable fabrication of vertical‐tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm-2. This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene–silicon heterostructures.

Research Area(s)

  • graphene, graphene-silicon junctions, high current density, tunneling transistors, vertical transistors

Citation Format(s)

High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures. / Liu, Yuan; Sheng, Jiming; Wu, Hao et al.
In: Advanced Materials, Vol. 28, No. 21, 01.06.2016, p. 4120-4125.

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review