High Performance Power-efficient Gate-based CAM for Reconfigurable computing

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)

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Detail(s)

Original languageEnglish
Title of host publication2019 15th International Conference on Mobile Ad-Hoc and Sensor Networks MSN 2019
Subtitle of host publicationProceedings
PublisherInstitute of Electrical and Electronics Engineers
Pages327-331
ISBN (Electronic)978-1-7281-5212-7
ISBN (Print)978-1-7281-5213-4
Publication statusPublished - Dec 2019

Publication series

NameProceedings - International Conference on Mobile Ad-Hoc and Sensor Networks, MSN

Conference

Title15th International Conference on Mobile Ad-Hoc and Sensor Networks, MSN 2019
LocationThe Hong Kong Polytechnic University Shenzhen Base
PlaceChina
CityShenzhen
Period11 - 13 December 2019

Abstract

Content-addressable memory (CAM) is a high-speed lookup memory, which searches the entire memory in parallel and provides address of the input search word. Internet of things (IoT) technology needs access control list filters, deployed using CAM, to reduce the flow of invalid data through the network. Field-programmable gate arrays (FPGAs) play an important role to provide the computational power to IoT nodes using ultra low power modern devices. CAMs are emulated in FPGAs using different memories, i.e., block RAM, distributed RAM, and flip-flops (FFs). FPGA-based CAMs have large power consumption due to the involvement of each CAM cell in parallel comparison. This work presents a bank-selective strategy for gate-based binary CAM on FPGA, which reduces the amount of comparisons and reduces power consumption on target FPGA device. For every input search key, only one bank is activated using gated-clock to compare the input key to corresponding stored rules. A sample of 512x36 of the proposed architecture with four banks is implemented on Xilinx Virtex-6 FPGA that consumes 42% less dynamic power compared to the best available CAM designs. Hardware resources of the proposed CAM design on target FPGA is reduced in terms of slice registers (SRs) and lookup tables (LUTs) by 7.9% and 8.8%, respectively, compared with the latest prior work.

Research Area(s)

  • Content addressable memory, Flip-flop, FPGA, Internet of Things, Reconfigurable computing

Citation Format(s)

High Performance Power-efficient Gate-based CAM for Reconfigurable computing. / Irfan, Muhammad; Ullah, Zahid; Cheung, Ray C. C.

2019 15th International Conference on Mobile Ad-Hoc and Sensor Networks MSN 2019: Proceedings. Institute of Electrical and Electronics Engineers, 2019. p. 327-331 9066055 (Proceedings - International Conference on Mobile Ad-Hoc and Sensor Networks, MSN).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)