High performance architecture for elliptic curve scalar multiplication based on FPGA

Elliptic curve scalar multiplication (ECSM) is the most important operation in elliptic curve cryptography (ECC). The study of its implementation performance and optimization has attracted great interests of researchers due to the rapid development and deployment of ECC recently. Focusing on designing high performance hardware architecture for this operation, first a digit-serial/parallel finite field multiplier with word width D is developed, which completes one multiplication over GF(2^m) in ⌈m/D⌉ cycles. Using this multiplier, a hardwired logic design for performing elliptic curve scalar multiplication over GF(2^m) is proposed. This architecture maximizes the parallelism that the projective coordinates version of the Montgomery scalar multiplication algorithm can achieve, and also shortens the maximum delay path. It completes one scalar multiplication over GF(2^m) in about (5m-6) ⌈m/D⌉ cycles. When implemented on Xilinx Virtex4-LX200 FPGA, using multipliers with word width 16, it occupies about 46% of all computation resources available, achieves a frequency of 225 MHz, and takes only 36 μs to complete one elliptic curve scalar multiplication operation for arbitrary elliptic curves, arbitrary points and integers over GF(2¹⁶³). This result outperforms all comparable FPGA-based elliptic curve scalar multipliers in the world. On the other hand, this architecture can be easily reconfigured to adapt different security levels and performance requirements.