Abstract
A hardware-based computational platform is developed to model the generalized Laguerre-Volterra (GLV) multiple-input multiple-output (MIMO) system which is essential in identification of the time-varying neural dynamics underlying spike activities. Time cost for model parameters estimation is greatly reduced by a significant enhancement of 3.1 × 10 3 x in data throughput of the Xilinx XC6VSX475T field programmable gate array (FPGA)-based system compared to a C model running on an Intel i7-860 Quad Core processor. The processing core consists of a first stage containing a vector convolution and MAC (multiply and accumulation) component; a second stage containing a prethreshold potential updating unit with an error approximation function component; and a third stage consisting of a gradient calculation unit. The hardware platform is scalable with the utilization of different number of processing units within each stage. It is also easily extendable into a multi-FPGA structure to further enhance the computational capability. A hardware IP library is proposed for versatile neural models and applications. The implementation of the self-reconfiguring platform and its applications to future research of neural dynamics are explored. © 2011 IEEE.
| Original language | English |
|---|---|
| Article number | 6112182 |
| Pages (from-to) | 489-501 |
| Journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
| Volume | 1 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - Dec 2011 |
Research Keywords
- Field programmable gate array (FPGA)
- generalized Laguerre-Volterra model
- IP library
- multiple-input multiple-output (MIMO) system
- neuroscience
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