High performance adder cell for low power pipelined multiplier

A high performance adder structure has been designed with a 0.5 microns N-well CMOS technology. The proposed circuit can operate well at 500 MHz with 5V supply and 330 MHz with 3V supply. It has better circuit performances in terms of power consumption, speed and area efficiency comparing with Complementary Pass Transistor logic and Differential Cascode Voltage Switch logic. The initial latency of a n-bit pipelined multiplication can be reduced to n from 2n with a two bits adder cell using the proposed circuit. It is suitable for low power low voltage pipelined multiplier implementation.